Rockchip RV1126 Datasheet V1.2

RV1126 is a high-performance vision processor SOC for IPC/CVR, eSPECially for AI related application It is based on quad-core arm Cortex-A7 32-bit core which integrates neoN and FPU. there is a 32KB I-cache and 32KB D-cache for each core and 512KB unified L2 cache The build-in NPU supports INT8/INT16 hybrid operation and computing power is up to Frameworks such as Tensor Flow/MXNet/Py Torch/ Caffe can be easily converted, eries of 2.0TOPs. In addition, with its strong compatibility, network models based on a

1.2 Features The features listed below which may or may not be present in actual product, may be subject to the third-party licensing requirements. Please contact Rockchip for actual product feature configurations and licensing requirements 1.2.1 Application Processor Quad-Core Cortex-A7 Full implementation of the aRm architecture v7-A instruction set ARM Neon Advanced SIMD Separately Integrated Neon and FPU 32KB L1 I-Cache and 32KB L1 D-Cache per cortex-A7 CPU e Unified 512KB L2 Cache for Quad-Core Cortex-A7 TrustZone technology supported Separate power domains for CPU core system to support internal power switch and externally turn on/ off based on different application scenario PD CPUO：1st Cortex-A7+ Neon FPU +L1 I/D Cache PD CPUl：2nd Cortex-A/+ Neon FPU+ Ll I/D Cache PD CPU2:3rd Cortex-A7 Neon FPU+ L1 I/D Cache I PD CPU3:4th Cortex-A7 +Neon FPU Ll I/D Cache One ISOlated voltage domain to support DVFS 1.2.2 video Input Interface Interface and video input processor Two mipi CSI/ LVDS/SubLVDS interfaces, 4 lanes each, 2. 5Gbps per lane One 8/10/12/16-bit standard DVP interface, up to 150MHz input data Support BT 601/BT 656 and BT 1120 VI interfaces Support the polarity of pixel_clk, hsync, vsync configurable