fpga的uart协议问题,贴有代码

可以正常收到信息，并将收到的值减1发回。
但是led在发送接收过程中始终不为1；且在rx.v中还有一点小问题
已在代码中用“错误：xxx“标出，大佬帮忙看下。

以下是顶层模块uart.v

`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 19:59:34 05/16/2020
// Design Name:
// Module Name: uart
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module uart(clk,tx,rx,rst,key1,led
);
input rst,rx,clk;
output tx;
reg [7:0] datatx;
wire [7:0] datarx;
reg [7:0] data;
reg[5:0] counttest;
reg flagtx;
wire flagrx;
wire sendover;
reg readover;
input key1;
output reg led;
reg [1:0] state,nextstate;
parameter idle=0 , read=1 ,send=2,buffer=3;

tx#(.clkrate(50),.baudrate(9600)) tx1(clk,rst,datatx,flagtx,tx,sendover);
rx#(.clkrate(50),.baudrate(9600)) rx1(clk,rst,datarx,flagrx,rx,readover);

always @ (*)
begin
if(!rst)
begin
nextstate=idle;
readover=0;
end

case(state)
idle:
begin
if(flagrx==1)
begin
nextstate=read;
readover=0;
end
else
begin
nextstate=idle;
readover=0;
end
end
read:
begin
if(!flagrx)
begin
nextstate=send;
readover=0;
end
else
begin
data=datarx-1;
readover=1;
nextstate=read;
end
end
send:
begin
datatx=data;
readover=0;
if(sendover)
nextstate=idle;
else
nextstate=send;
end
default:
begin
nextstate=idle;
readover=0;
end

endcase
end

always @ (*)
begin
if(!rst)
flagtx=0;
else if (nextstate==send && state!=nextstate)
flagtx=1;
else if(state!=send)
flagtx=0;
end

always @ (posedge clk,negedge rst)
begin
if(!rst)
state<=idle;

else
state<=nextstate;
end

always @ (*)
begin
if(!rst)
led=0;
else if (state!=idle)
led=1; //问题：灯不亮
else
led=led;
end

always @(posedge clk ,negedge rst)
if(!rst)
counttest<=0;
else if (state==read)
counttest<=counttest+1;
endmodule

以下是接收模块rx.v

//以下是接收模块rx.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:18:30 05/16/2020
// Design Name:
// Module Name: rx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module rx #(parameter clkrate=50,parameter baudrate=9600
)(clk,rst,datarec,flag,rxport,readover);
input clk,rst;
output reg[7:0]datarec;
output reg flag;
input rxport;
input readover;

parameter counter_counts=clkrate*1000000/baudrate;

parameter idle=0 , start=1 , receive=2 , stop=3;

reg[1:0]state;
reg[1:0]nextstate;

reg [20:0] counter;

reg [2:0] rec_bit;

always @ (*)
begin
if(!rst)
nextstate=idle;

case(state)
idle:
begin
if(rxport==0)
nextstate=start;
else
nextstate=idle;
end
start:
begin
if(counter>=counter_counts-1)
nextstate=receive;
else
nextstate=start;
end
receive:
begin
if(rec_bit==7 && counter>=counter_counts-1)
nextstate=stop;
else
nextstate=receive;
end
stop:
begin
if(counter>=counter_counts-1)
nextstate=idle;
else
nextstate=stop;
end
default:
nextstate=idle;
endcase

end

always @ (posedge clk,negedge rst)
begin
if(!rst)
state<=idle;
else
state<=nextstate;
end

always @ (posedge clk,negedge rst)
begin
if(!rst)
counter<=0;
else if (nextstate!=state || (state==receive && counter>=counter_counts-1))
counter<=0;
else
counter<=counter+1;
end

always @ (posedge clk,negedge rst)
begin
if(!rst)
datarec=0;
else if(state==receive && counter==counter_counts>>1) //问题：改成counter>5 && counter<counter_counts-5则读不出来数据，读取乱码
begin
if (rec_bit==0)
datarec[0]=rxport;
else if(rec_bit==1)
datarec[1]=rxport;
else if(rec_bit==2)
datarec[2]=rxport;
else if(rec_bit==3)
datarec[3]=rxport;
else if(rec_bit==4)
datarec[4]=rxport;
else if(rec_bit==5)
datarec[5]=rxport;
else if(rec_bit==6)
datarec[6]=rxport;
else if(rec_bit==7)
datarec[7]=rxport;
end
end

always @ (posedge clk,negedge rst)
begin
if(!rst)
rec_bit<=0;
else if(state!=receive)
rec_bit<=0;
else if (counter>=counter_counts-1)
rec_bit<=rec_bit+1;
else
rec_bit<=rec_bit;
end

always @ (*)
begin
if(!rst)
flag=0;
else if(state==stop && counter==counter_counts-1)
flag=1;
else if (readover )
flag=0;
end

endmodule

以下是发送模块tx.v

\以下是发送模块tx.v
`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company:
// Engineer:
//
// Create Date: 20:18:21 05/16/2020
// Design Name:
// Module Name: tx
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//////////////////////////////////////////////////////////////////////////////////
module tx #(parameter clkrate=50,parameter baudrate=9600
)
(clk,rst,datat,flag,txport,sendover);

input clk,rst;
input [7:0] datat;
output reg txport;
input flag;
output reg sendover;
reg [1:0] state;
reg [1:0] nextstate;
reg [20:0] counter;
reg [2:0] sending_bit;
parameter idle=2’d0;
parameter start=2’d1;//qihiwei
parameter send=2’d2;//shuju

parameter stop=2’d3;//jieshuwei

parameter counter_counts=clkrate*1000000/baudrate;

always @ (posedge clk,negedge rst)
begin
if(!rst)
state<=idle;
//flag=’b0;
else
state<=nextstate;
end

always @ (*)
begin
case (state)
idle:
begin
if(!rst)
nextstate=idle;
else if(flag)
nextstate=start;
else
nextstate=idle;
end
start:
begin
if (counter>=counter_counts-1)
nextstate=send;
else
nextstate=start;
end
send:
begin
if (counter>=counter_counts-1 && sending_bit==7)
nextstate=stop;
else
nextstate=send;
end
stop:
begin
if (counter>=counter_counts-1)
nextstate=idle;
else
nextstate=stop;
end
endcase
end

always @ (posedge clk,negedge rst)
begin
if(!rst)
counter<=0;
else if (nextstate!=state || (state==send && counter>=counter_counts-1))
counter<=0;
else
counter<=counter+1;
end

always @ (posedge clk or negedge rst)
begin
if(!rst)
sending_bit=0;
else if(state!=send)
sending_bit=0;
else if (counter>=counter_counts-1)
sending_bit=sending_bit+1;
else
sending_bit=sending_bit;
end

always @ (posedge clk or negedge rst)
begin
if(!rst)
txport<=1;
else
case(state)
idle,stop:
txport<=1;
start:
txport<=0;
send:
begin
if (sending_bit==0)
txport<=datat[0];
else if (sending_bit==1)
txport<=datat[1];
else if (sending_bit==2)
txport<=datat[2];
else if (sending_bit==3)
txport<=datat[3];
else if (sending_bit==4)
txport<=datat[4];
else if (sending_bit==5)
txport<=datat[5];
else if (sending_bit==6)
txport<=datat[6];
else if (sending_bit==7)
txport<=datat[7];
end
endcase
end

always @ (*)
begin
if(!rst)
sendover=0;
else if (state==stop && counter==counter_counts-1)
sendover=1;
else if(state== idle && flag==1)
sendover=0;
else if (state== idle && flag==0)
sendover=1;
end

endmodule