2571
- 收藏
- 点赞
- 分享
- 举报
HI3559CV100+IMX178开发配置经验总结
一、HI3559C主芯片配置——MIPI_RX配置
◆ Supports I/O switching
Low voltage LVDS (150 mVp-p) serial (4 ch / 8 ch / 10 ch switching) DDR output
combo_dev_attr_t LVDS_4lane_SENSOR_IMX178_12BIT_1080p_ATTR =
{
/* input mode */
.devno = 0,
.input_mode = INPUT_MODE_LVDS,
.data_rate = MIPI_DATA_RATE_X1,
.img_rect = {0, 0, 1920, 1080},
{
.lvds_attr = {
DATA_TYPE_RAW_12BIT,
HI_WDR_MODE_NONE,
LVDS_SYNC_MODE_SAV,
.vsync_attr = {LVDS_VSYNC_NORMAL, 0, 0},
.fid_attr = {LVDS_FID_NONE, HI_TRUE},
LVDS_ENDIAN_BIG,
LVDS_ENDIAN_BIG,
.lane_id = {0, 1, 2, 3, -1, -1, -1, -1},
.sync_code = {
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}},
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}},
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}},
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}},
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}},
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}},
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}},
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}}
}
}
}
};
二、HI3559C主芯片配置VI配置
mpp/sample/common/sample_comm_vi.c中修改VI相关配置
VI DEV配置,主要配置输入接口LVDS、掩码0xFFF00000、图像格式RGB、分辨率1920*1080
VI_DEV_ATTR_S DEV_ATTR_IMX178_LVDS_BASE =
{
/* interface mode */
VI_MODE_LVDS,
/* multiplex mode */
VI_WORK_MODE_1Multiplex,
/* r_mask g_mask b_mask*/
{0xFFF00000, 0x0},
/* progessive or interleaving */
VI_SCAN_PROGRESSIVE,
/*AdChnId*/
{-1, -1, -1, -1},
/*enDataSeq, only support yuv*/
VI_DATA_SEQ_YUYV,
/* synchronization information */
{
/*port_vsync port_vsync_neg port_hsync port_hsync_neg */
VI_VSYNC_PULSE, VI_VSYNC_NEG_LOW, VI_HSYNC_VALID_SINGNAL,VI_HSYNC_NEG_HIGH,VI_VSYNC_VALID_SINGAL,VI_VSYNC_VALID_NEG_HIGH,
/*hsync_hfb hsync_act hsync_hhb*/
{0, 1280, 0,
/*vsync0_vhb vsync0_act vsync0_hhb*/
0, 720, 0,
/*vsync1_vhb vsync1_act vsync1_hhb*/
0, 0, 0}
},
/* input data type */
VI_DATA_TYPE_RGB,
/* bRever */
HI_FALSE,
{1920 , 1080},
{
{
{1920 , 1080},
},
{
VI_REPHASE_MODE_NONE,
VI_REPHASE_MODE_NONE
}
},
{
WDR_MODE_NONE,
1080
},
DATA_RATE_X1
};
I2C写寄存器写入方式如下
int imx178_write_register(VI_PIPE ViPipe, int addr, int data)
{
if (0 > g_fd[ViPipe])
{
return HI_SUCCESS;
}
int idx = 0;
int ret;
char buf[8];
if (imx178_addr_byte == 2)
{
buf[idx] = (addr >> 8) & 0xff;
idx++;
buf[idx] = addr & 0xff;
idx++;
}
else
{
buf[idx] = addr & 0xff;
idx++;
}
if (imx178_data_byte == 2)
{
buf[idx] = (data >> 8) & 0xff;
idx++;
buf[idx] = data & 0xff;
idx++;
}
else
{
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, (imx178_addr_byte + imx178_data_byte));
if (ret < 0)
{
ISP_TRACE(HI_DBG_ERR, "I2C_WRITE DATA error!\n");
return HI_FAILURE;
}
return HI_SUCCESS;
}
未完待续…………
◆ Supports I/O switching
Low voltage LVDS (150 mVp-p) serial (4 ch / 8 ch / 10 ch switching) DDR output
combo_dev_attr_t LVDS_4lane_SENSOR_IMX178_12BIT_1080p_ATTR =
{
/* input mode */
.devno = 0,
.input_mode = INPUT_MODE_LVDS,
.data_rate = MIPI_DATA_RATE_X1,
.img_rect = {0, 0, 1920, 1080},
{
.lvds_attr = {
DATA_TYPE_RAW_12BIT,
HI_WDR_MODE_NONE,
LVDS_SYNC_MODE_SAV,
.vsync_attr = {LVDS_VSYNC_NORMAL, 0, 0},
.fid_attr = {LVDS_FID_NONE, HI_TRUE},
LVDS_ENDIAN_BIG,
LVDS_ENDIAN_BIG,
.lane_id = {0, 1, 2, 3, -1, -1, -1, -1},
.sync_code = {
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}},
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}},
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}},
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}},
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}},
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}},
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}},
{{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0},
{0xab0, 0xb60, 0x800, 0x9d0}}
}
}
}
};
二、HI3559C主芯片配置VI配置
mpp/sample/common/sample_comm_vi.c中修改VI相关配置
VI DEV配置,主要配置输入接口LVDS、掩码0xFFF00000、图像格式RGB、分辨率1920*1080
VI_DEV_ATTR_S DEV_ATTR_IMX178_LVDS_BASE =
{
/* interface mode */
VI_MODE_LVDS,
/* multiplex mode */
VI_WORK_MODE_1Multiplex,
/* r_mask g_mask b_mask*/
{0xFFF00000, 0x0},
/* progessive or interleaving */
VI_SCAN_PROGRESSIVE,
/*AdChnId*/
{-1, -1, -1, -1},
/*enDataSeq, only support yuv*/
VI_DATA_SEQ_YUYV,
/* synchronization information */
{
/*port_vsync port_vsync_neg port_hsync port_hsync_neg */
VI_VSYNC_PULSE, VI_VSYNC_NEG_LOW, VI_HSYNC_VALID_SINGNAL,VI_HSYNC_NEG_HIGH,VI_VSYNC_VALID_SINGAL,VI_VSYNC_VALID_NEG_HIGH,
/*hsync_hfb hsync_act hsync_hhb*/
{0, 1280, 0,
/*vsync0_vhb vsync0_act vsync0_hhb*/
0, 720, 0,
/*vsync1_vhb vsync1_act vsync1_hhb*/
0, 0, 0}
},
/* input data type */
VI_DATA_TYPE_RGB,
/* bRever */
HI_FALSE,
{1920 , 1080},
{
{
{1920 , 1080},
},
{
VI_REPHASE_MODE_NONE,
VI_REPHASE_MODE_NONE
}
},
{
WDR_MODE_NONE,
1080
},
DATA_RATE_X1
};
I2C写寄存器写入方式如下
int imx178_write_register(VI_PIPE ViPipe, int addr, int data)
{
if (0 > g_fd[ViPipe])
{
return HI_SUCCESS;
}
int idx = 0;
int ret;
char buf[8];
if (imx178_addr_byte == 2)
{
buf[idx] = (addr >> 8) & 0xff;
idx++;
buf[idx] = addr & 0xff;
idx++;
}
else
{
buf[idx] = addr & 0xff;
idx++;
}
if (imx178_data_byte == 2)
{
buf[idx] = (data >> 8) & 0xff;
idx++;
buf[idx] = data & 0xff;
idx++;
}
else
{
buf[idx] = data & 0xff;
idx++;
}
ret = write(g_fd[ViPipe], buf, (imx178_addr_byte + imx178_data_byte));
if (ret < 0)
{
ISP_TRACE(HI_DBG_ERR, "I2C_WRITE DATA error!\n");
return HI_FAILURE;
}
return HI_SUCCESS;
}
未完待续…………
我来回答
回答0个
时间排序
认可量排序
暂无数据
或将文件直接拖到这里
悬赏:
E币
网盘
* 网盘链接:
* 提取码:
悬赏:
E币
Markdown 语法
- 加粗**内容**
- 斜体*内容*
- 删除线~~内容~~
- 引用> 引用内容
- 代码`代码`
- 代码块```编程语言↵代码```
- 链接[链接标题](url)
- 无序列表- 内容
- 有序列表1. 内容
- 缩进内容
- 图片![alt](url)
相关问答
-
2020-03-14 17:43:56
-
2018-12-14 12:28:34
-
2018-08-28 11:24:39
-
2016-05-17 20:42:57
-
2016-06-15 14:54:55
-
2019-01-07 15:10:50
-
2015-10-26 09:42:06
-
2020-03-11 11:30:31
-
2019-01-16 16:58:39
-
2019-11-19 14:31:04
-
2016-08-22 08:56:42
-
2020-07-11 22:00:18
-
2019-05-28 15:11:03
-
2015-08-05 12:17:17
-
2019-08-22 20:08:20
-
2018-12-05 20:09:31
-
02019-08-27 08:53:39
-
2018-12-26 15:22:16
-
2018-05-22 14:31:48
无更多相似问答 去提问
点击登录
-- 积分
-- E币
提问
—
收益
—
被采纳
—
我要提问
切换马甲
上一页
下一页
悬赏问答
-
5Hi3516CV610 如何使用SD卡升级固件
-
5cat /dev/logmpp 报错 <3>[ vi] [func]:vi_send_frame_node [line]:99 [info]:vi pic queue is full!
-
50如何获取vpss chn的图像修改后发送至vo
-
5FPGA通过Bt1120传YUV422数据过来,vi接收不到数据——3516dv500
-
50SS928 运行PQtools 拼接 推到设备里有一半画面会异常
-
53536AV100的sample_vdec输出到CVBS显示
-
10海思板子mpp怎么在vi阶段改变视频数据尺寸
-
10HI3559AV100 多摄像头同步模式
-
9海思ss928单路摄像头vio中加入opencv处理并显示
-
10EB-RV1126-BC-191板子运行自己编码的程序
举报反馈
举报类型
- 内容涉黄/赌/毒
- 内容侵权/抄袭
- 政治相关
- 涉嫌广告
- 侮辱谩骂
- 其他
详细说明
提醒
你的问题还没有最佳答案,是否结题,结题后将扣除20%的悬赏金
取消
确认
提醒
你的问题还没有最佳答案,是否结题,结题后将根据回答情况扣除相应悬赏金(1回答=1E币)
取消
确认