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先进的智能IP摄像机Soc 海思 Hi3519AV100资料可咨询
先进的智能IP摄像机Soc 海思 Hi3519AV100资料需要的,可咨询
roman, HelveticaNeue-Light, Helvetica Neue, arial, Hiragino Sans GB, 冬青黑体, MICrosoft YaHei New, Microsoft Yahei, 微软雅黑, 宋体, SIMSun, STXihei, 华文细黑, sans-serif">海思 hi3519AV100主要特点:双核[email]2xA53@1.4GHz4K[/email] @ 60fps H.265编解码器2chn / 4chn StitchingvDSP @ 630MHz和NNIE引擎PCI-e 2.0 + USB2.0高速存储
Hi3519A V100 4K Smart IP camera SoC
Breif Data Sheet
Issue&nBSP; 02
Date 2018-06-20
Copyright © HiSilicon Technologies Co., Ltd. 2018. All rights reserved.No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of HiSilicon Technologies Co., Ltd.
file:///C:\Users\admin\AppData\Local\Temp\ksohtml8796\wps2.pngTrademarks and Permissions
file:///C:\Users\admin\AppData\Local\Temp\ksohtml8796\wps3.jpg, , and other HiSilicon icons are trademarks of HiSilicon Technologies Co., Ltd.
All other trademarks and trade names mentioned in this document are the property of their reSPECtive holders.
Notice
The purchased products, services and features are stipulated by the contract made between HiSilicon and the customer. All or part of the products, services and features described in this document may not be within the purchase scope or the usage scope. Unless otherwise specified in the contract, all statements, information, and recommendations in this document are provided "AS IS" without warranties, guarantees or representations of any kind, either express or implied.
The information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute a warranty of any kind, express or implied.
HiSilicon Technologies Co., Ltd.
Address: New R&D Center, Wuhe Road, Bantian, Longgang District, Shenzhen 518129 P. R. China
Introduction
Hi3519A V100 is a high-performance and low-power 4K Smart IP Camera SoC designed for IP cameras, action cameras, panoramic cameras, rear view mirrors, and UAVs. Hi3519A V100 introduces H.265/H.264 encoding and decoding, with performance up to 4K x 2K@60 fps and 1080p@240 fps.
Integrating with the HiSilicon fourth-generation ISP, Hi3519A V100 provides WDR, multi-level NR, 6DoF DIS, and multiple image enhancement and correction algorithms, ensuring professional image quality. Hi3519A V100 also supports 4K raw data output, facilitating post editing. With the advanced low-power process and architecture design, Hi3519A V100 provides users with long-lasting Battery life.
Hi3519A V100 integrates a powerful programmable neural network inference engine and a vector DSP, backing the application of multiple intelligent algorithms.
Hi3519A V100 supports multi-sensor inputs and introduces a built-in high-performance AVS engine to implement 4K 2-pipe to 4-pipe real-time panoramic video stitching.
With the hardware-based 6DoF DIS, Hi3519A V100 has reduced its dependence on the mechanical head during 4K@60 fps video recording.
Hi3519A V100 features efficient and ample computing resources to assist customers in developing industry and consumer applications. Backed by the dual-core A53 processor and the DSP, Hi3519A V100 offers the dual-system solution, enabling fast startup, real-time performance, and connections with rich peripheral drives.
Hi3519A V100 uses the advanced 12 nm low-power process and miniaturization package and supports DDR4/LPDDR4 SDRAMs, allowing the product miniaturization design.
With the stable and easy-to-use mobile SDK design provided by HiSilicon, Hi3519A V100 can assist customers in rapid product mass production.
Key Features
• Low Power
−
1.9 W power consumption in a typical scenario for 4K x
2K (3840 x 2160)@30 fps H.265 encoding+neural network
algorithm
• −SVP
− A neural network inference engine (NNIE), a high-
− performance DSP, and multiple CV acceleration
− engines that facilitate customers' algorithm development
for achieving product differentiation
Multiple neural network options
2.0 TOPS computing performance Complete APIs and toolchains Multiple applications such as face
detection/recognition and target detection/tracking
• 4K@60 fps Encoding
4K x 2K (3840 x 2160)@60 fps or 1080p@240 fps H.265/H.264 encoding
• Multi-Sensor Inputs
Up to 5-channel sensor inputs, supporting applications such as panoramic camera and UAVs
• Hardware-based Multi-Channel Video Stitching 2-channel 3K x 3K (3000 x 3000)@30 fps or 4-channel 1080p@30 fps stitching and recording
• High-Speed Interface
PCIe, USB 3.0, and SDIO 3.0 interfaces that facilitate customers' extension of external functional modules
Key SpecificationsProcessor Core
• Dual-core arm [email]Cortex-A53@1.4GHz[/email], 32 KB I-cache, 32 KB D-cache or 256 KB L2-cache
• Neon acceleration and integrated FPU
DSP
• Integrated Tensilica Vision P6 DSP@630 MHz
• 32 KB I-cache, 32 KB I-RAM, and 512 KB D-RAM
• 0.3 TOPS neural network computing performance
• Huawei LiteOS
NNIE
• Multiple neural network options, such as AlexNet, VGG, ResNet, and GoogleNet
• Multiple neural network options for target detection, such as the Faster R-CNN, SSD, and YOLOv2
• 2.0 TOPS neural network computing performance
• Complete APIs and tool chains (compilers and simulators) to adapt to customized networks
Video Encoding and Decoding
• H.265 main profile, level 5.1
• H.264 baseline/main/high profile, level 5.1
• I-/P-/B-slice supported for H.264/H.265 encoding and
d−ecoding
• B−aseline JPEG
• M− aximum resolution for H.264/H.265 encoding and
decoding: 8192 x 8192
• H.265/H.264 encoding and decoding performance: 3840 x 2160@60 fps+720p@30 fps encoding 3840 x 2160@60 fps decoding
3840 x 2160@30 fps encoding+3840 x 2160@30 fps decoding
• Maximum resolution for JPEG encoding and decoding: 8192 x 8192
• Maximum JPEG encoding and decoding performance: 16 MP (4608 x 3456)@30 fps
• Multiple bit rate control modes, such as CBR, VBR, AVBR, FixQp, and QpMap
• Up to a bit rate of 120 Mbit/s for H.265 encoding outputs and 200 Mbit/s for H.264 encoding outputs
• Encoding of up to eight ROIs
VI Interface
• 12-lane image sensor serial inputs, as well as mipi, sub- LVDS, Hispi, and SLVS-EC interfaces
• Up to 5-channel sensor serial inputs and multiple combination modes: 12-lane, 8-lane+4-lane, or 4-lane+4 x 2-lane
• Maximum input resolution: 7680 x 4320
• 10-/12-/14-bit Bayer RGB DC timing VI
• BT.656 and BT.1120 VI
1–channel to 4-channel YUV inputs through the MIPI virtual channels
ISP and Image Processing
• Multi-channel TDM to process multi-sensor video inputs
• Adjustable 3A functions (AE, AWB, and AF)
• FPN removal
• 2-frame WDR exposure, local tone mapping, strong light suppression, and backlight compensation
• Defect pixel correction and lens shADIng correction
• Multi-level 3DNR, which removes motion smearing and chroma noise and provides excellent image effects in low illumination
• 3D-LUT color adjustment
• Image dynamic contrast enhancement and EDGE enhancement
• CAC and purple fringe removal
• Dehaze
• 6DoF DIS and rolling shutter correction
• LGDC and fisheye correction
• Image rotation by 90° or 270°
• Image mirroring and flipping
• Multi-channel 1/15.5x–16x scaling outputs
• OSD overlaying of up to eight regions before encoding
• ISP adjustment tool on the PC
2D Graphics Processing
• BitBlt operation
• Line drawing
• Alpha blending
• Color key
• CSC
−
Hardware Accelerated Engine for Video
Stitc−hing
• 2-channel and 4-channel AVS
• Stitching performance:
2-channel 3000 x 3000@30 fps VI and 3840 x 2160@30 fps VO
4-channel 1080 x 1920@30 fps VI and 3840 x 2160@30 fps VO
VO Interface
• HDMI 2.0, supporting up to 4K x 2K (4096 x 2160)@60
f−ps outputs
• 4-lane MIPI DSI, supporting up to 1080p@60 fps outputs
• 6−-/8-/16-/24-bit digital LCD/BT.656/BT.1120 interface,
s−upporting up to 1080p@60 fps RGB/YUV outputs
• Two independent HD VO channels (DHD 0 and DHD 1):
Any two interfaces can be used for the display of different sources.
DHD 0 supports 36-picture split display. DHD 1 supports 16-picture split display.
• One PIP layer, which can be overlaid with DHD 0 or DHD 1
• Two full-screen GUI graphics layers in ARGB1555 or ARGB8888 format for DHD 0 and DHD 1
• One hardware cursor layer in ARGB1555 or ARGB8888 format (configurable), supporting a maximum resolution
of 256 x 256
• One scaling WBC channel
CV Hardware Accelerated Engine
• Hardware acceleration for binocular depth map computing, supporting the processing performance up to 720p@30 fps
• Hardware acceleration for IVE 2.1 intelligent operators for feature point detection, optical flow, and computer morphology processing, and so on
audio Interface
• Integrated audio codec, supporting 16-bit audio inputs and outputs
• Dual-channel differential MIC inputs for reducing the background noise
• I2S interface for 8-channel audio TDM inputs and dual- channel audio outputs (mutually exclusive with the built- in audio codec)
• HDMI audio output
Audio Encoding and Decoding
• Voice encoding and decoding complying with multiple protocols by software
• Audio encoding in formats such as G.711, G.726, and
file:///C:\Users\admin\AppData\Local\Temp\ksohtml8796\wps4.png−
AAC
−
VQE
−
Netw− ork Interface
• One GE interface:
RGMII and RMII modes
10/100 Mbit/s half-duplex or full-duplex 1000 Mbit/s full-duplex
TSO for reducing the CPU usage
Security Engine
• AES, DES, and 3DES algorithms implemented by using hardware
• RSA1024/2048/3072/4096 signature verification algorithm implemented by using hardware
• HASH-SHA1/224/256/384/512 and
HMAC_SHA1/224/256/384/512 tamper proofing algorithms implemented by using hardware
• file:///C:\Users\admin\AppData\Local\Temp\ksohtml8796\wps5.pngIntegrated 32-kbit OTP storage space and hardware random number generator
• file:///C:\Users\admin\AppData\Local\Temp\ksohtml8796\wps6.pngSecure boot
• memory and I/O security ISOlation
Peri−pheral Interface
• −Two SDIO 3.0 interfaces:
− SDIO 0 supports the SDXC card.
SDIO 1 supports the Wi-Fi module.
• One USB 3.0/PCIe 2.0 multiplexing port USB 3.0 only or PCIe 2.0 X1+USB 2.0.
RC and endpoint supported as the PCIe 2.0 interface Configurable USB host/device mode as the USB 3.0 interface
• One USB 2.0 port, supporting configurable host/device mode
• Internal POR signal output and external reset input
• Independent battery for the built-in RTC
• Integrated 4-channel LSADC
• Nine UART interfaces (Some pins are multiplexed with other pins.)
• Multiple I2C, SPI, and GPIO interfaces
• file:///C:\Users\admin\AppData\Local\Temp\ksohtml8796\wps7.pngOne IR interface
• Eight PWM interfaces (Some pins are multiplexed with other pins.)
−
External Memory Interface
• 3−2-bit DDR4/LPDDR4 SDRAM interface
− Maximum frequency of 1333 MHz for the
− DDR4/LPDDR4 SDRAM
Maximum DDR address space of 3.5 GB
• S−I NOR flash interface
− 1-/2-/4-line mode
− 3-/4-byte address mode
− Maximum capacity of 256 MB
• SPI NAND flash interface
− SLC flash
− 2 KB/4 KB page size
− 8-/24-bit ECC (unit: KB)
− Maximum capacity of 1 GB
• N− AND flash interface
8-bit data width
− SLC flash
− 2 KB/4 KB page size
8-/16-/24-bit ECC (unit: KB)
Maximum capacity of 1 GB
• EMMC 5.1 interface HS400
Maximum capacity of 2 TB
Configurable Boot Modes
• Booting from the BOOTROM
• Booting from the SPI NOR flash
• Booting from the SPI NAND flash
• Booting from the NAND flash
• Booting from an eMMC
Multiple Image Burning Modes
• Image burning through UART 0
• Image burning through an SD card
• Image burning through a USB device
SDK
• file:///C:\Users\admin\AppData\Local\Temp\ksohtml8796\wps8.pnglinux SMP
• Linux+Huawei LiteOS dual-system solution
• High-performance H.265 IOS/android decoding library
Phys−ical Specifications
• Power consumption
1.9 W power consumption in a typical scenario for 4K x 2K (3840 x 2160)@30 fps encoding+neural network algorithm
Multi-level power saving mode
• Operating voltages
roman, HelveticaNeue-Light, Helvetica Neue, arial, Hiragino Sans GB, 冬青黑体, MICrosoft YaHei New, Microsoft Yahei, 微软雅黑, 宋体, SIMSun, STXihei, 华文细黑, sans-serif">海思 hi3519AV100主要特点:双核[email]2xA53@1.4GHz4K[/email] @ 60fps H.265编解码器2chn / 4chn StitchingvDSP @ 630MHz和NNIE引擎PCI-e 2.0 + USB2.0高速存储
Hi3519A V100 4K Smart IP camera SoC
Breif Data Sheet
Issue&nBSP; 02
Date 2018-06-20
Copyright © HiSilicon Technologies Co., Ltd. 2018. All rights reserved.No part of this document may be reproduced or transmitted in any form or by any means without prior written consent of HiSilicon Technologies Co., Ltd.
file:///C:\Users\admin\AppData\Local\Temp\ksohtml8796\wps2.pngTrademarks and Permissions
file:///C:\Users\admin\AppData\Local\Temp\ksohtml8796\wps3.jpg, , and other HiSilicon icons are trademarks of HiSilicon Technologies Co., Ltd.
All other trademarks and trade names mentioned in this document are the property of their reSPECtive holders.
Notice
The purchased products, services and features are stipulated by the contract made between HiSilicon and the customer. All or part of the products, services and features described in this document may not be within the purchase scope or the usage scope. Unless otherwise specified in the contract, all statements, information, and recommendations in this document are provided "AS IS" without warranties, guarantees or representations of any kind, either express or implied.
The information in this document is subject to change without notice. Every effort has been made in the preparation of this document to ensure accuracy of the contents, but all statements, information, and recommendations in this document do not constitute a warranty of any kind, express or implied.
HiSilicon Technologies Co., Ltd.
Address: New R&D Center, Wuhe Road, Bantian, Longgang District, Shenzhen 518129 P. R. China
Introduction
Hi3519A V100 is a high-performance and low-power 4K Smart IP Camera SoC designed for IP cameras, action cameras, panoramic cameras, rear view mirrors, and UAVs. Hi3519A V100 introduces H.265/H.264 encoding and decoding, with performance up to 4K x 2K@60 fps and 1080p@240 fps.
Integrating with the HiSilicon fourth-generation ISP, Hi3519A V100 provides WDR, multi-level NR, 6DoF DIS, and multiple image enhancement and correction algorithms, ensuring professional image quality. Hi3519A V100 also supports 4K raw data output, facilitating post editing. With the advanced low-power process and architecture design, Hi3519A V100 provides users with long-lasting Battery life.
Hi3519A V100 integrates a powerful programmable neural network inference engine and a vector DSP, backing the application of multiple intelligent algorithms.
Hi3519A V100 supports multi-sensor inputs and introduces a built-in high-performance AVS engine to implement 4K 2-pipe to 4-pipe real-time panoramic video stitching.
With the hardware-based 6DoF DIS, Hi3519A V100 has reduced its dependence on the mechanical head during 4K@60 fps video recording.
Hi3519A V100 features efficient and ample computing resources to assist customers in developing industry and consumer applications. Backed by the dual-core A53 processor and the DSP, Hi3519A V100 offers the dual-system solution, enabling fast startup, real-time performance, and connections with rich peripheral drives.
Hi3519A V100 uses the advanced 12 nm low-power process and miniaturization package and supports DDR4/LPDDR4 SDRAMs, allowing the product miniaturization design.
With the stable and easy-to-use mobile SDK design provided by HiSilicon, Hi3519A V100 can assist customers in rapid product mass production.
Key Features
• Low Power
−
1.9 W power consumption in a typical scenario for 4K x
2K (3840 x 2160)@30 fps H.265 encoding+neural network
algorithm
• −SVP
− A neural network inference engine (NNIE), a high-
− performance DSP, and multiple CV acceleration
− engines that facilitate customers' algorithm development
for achieving product differentiation
Multiple neural network options
2.0 TOPS computing performance Complete APIs and toolchains Multiple applications such as face
detection/recognition and target detection/tracking
• 4K@60 fps Encoding
4K x 2K (3840 x 2160)@60 fps or 1080p@240 fps H.265/H.264 encoding
• Multi-Sensor Inputs
Up to 5-channel sensor inputs, supporting applications such as panoramic camera and UAVs
• Hardware-based Multi-Channel Video Stitching 2-channel 3K x 3K (3000 x 3000)@30 fps or 4-channel 1080p@30 fps stitching and recording
• High-Speed Interface
PCIe, USB 3.0, and SDIO 3.0 interfaces that facilitate customers' extension of external functional modules
Key SpecificationsProcessor Core
• Dual-core arm [email]Cortex-A53@1.4GHz[/email], 32 KB I-cache, 32 KB D-cache or 256 KB L2-cache
• Neon acceleration and integrated FPU
DSP
• Integrated Tensilica Vision P6 DSP@630 MHz
• 32 KB I-cache, 32 KB I-RAM, and 512 KB D-RAM
• 0.3 TOPS neural network computing performance
• Huawei LiteOS
NNIE
• Multiple neural network options, such as AlexNet, VGG, ResNet, and GoogleNet
• Multiple neural network options for target detection, such as the Faster R-CNN, SSD, and YOLOv2
• 2.0 TOPS neural network computing performance
• Complete APIs and tool chains (compilers and simulators) to adapt to customized networks
Video Encoding and Decoding
• H.265 main profile, level 5.1
• H.264 baseline/main/high profile, level 5.1
• I-/P-/B-slice supported for H.264/H.265 encoding and
d−ecoding
• B−aseline JPEG
• M− aximum resolution for H.264/H.265 encoding and
decoding: 8192 x 8192
• H.265/H.264 encoding and decoding performance: 3840 x 2160@60 fps+720p@30 fps encoding 3840 x 2160@60 fps decoding
3840 x 2160@30 fps encoding+3840 x 2160@30 fps decoding
• Maximum resolution for JPEG encoding and decoding: 8192 x 8192
• Maximum JPEG encoding and decoding performance: 16 MP (4608 x 3456)@30 fps
• Multiple bit rate control modes, such as CBR, VBR, AVBR, FixQp, and QpMap
• Up to a bit rate of 120 Mbit/s for H.265 encoding outputs and 200 Mbit/s for H.264 encoding outputs
• Encoding of up to eight ROIs
VI Interface
• 12-lane image sensor serial inputs, as well as mipi, sub- LVDS, Hispi, and SLVS-EC interfaces
• Up to 5-channel sensor serial inputs and multiple combination modes: 12-lane, 8-lane+4-lane, or 4-lane+4 x 2-lane
• Maximum input resolution: 7680 x 4320
• 10-/12-/14-bit Bayer RGB DC timing VI
• BT.656 and BT.1120 VI
1–channel to 4-channel YUV inputs through the MIPI virtual channels
ISP and Image Processing
• Multi-channel TDM to process multi-sensor video inputs
• Adjustable 3A functions (AE, AWB, and AF)
• FPN removal
• 2-frame WDR exposure, local tone mapping, strong light suppression, and backlight compensation
• Defect pixel correction and lens shADIng correction
• Multi-level 3DNR, which removes motion smearing and chroma noise and provides excellent image effects in low illumination
• 3D-LUT color adjustment
• Image dynamic contrast enhancement and EDGE enhancement
• CAC and purple fringe removal
• Dehaze
• 6DoF DIS and rolling shutter correction
• LGDC and fisheye correction
• Image rotation by 90° or 270°
• Image mirroring and flipping
• Multi-channel 1/15.5x–16x scaling outputs
• OSD overlaying of up to eight regions before encoding
• ISP adjustment tool on the PC
2D Graphics Processing
• BitBlt operation
• Line drawing
• Alpha blending
• Color key
• CSC
−
Hardware Accelerated Engine for Video
Stitc−hing
• 2-channel and 4-channel AVS
• Stitching performance:
2-channel 3000 x 3000@30 fps VI and 3840 x 2160@30 fps VO
4-channel 1080 x 1920@30 fps VI and 3840 x 2160@30 fps VO
VO Interface
• HDMI 2.0, supporting up to 4K x 2K (4096 x 2160)@60
f−ps outputs
• 4-lane MIPI DSI, supporting up to 1080p@60 fps outputs
• 6−-/8-/16-/24-bit digital LCD/BT.656/BT.1120 interface,
s−upporting up to 1080p@60 fps RGB/YUV outputs
• Two independent HD VO channels (DHD 0 and DHD 1):
Any two interfaces can be used for the display of different sources.
DHD 0 supports 36-picture split display. DHD 1 supports 16-picture split display.
• One PIP layer, which can be overlaid with DHD 0 or DHD 1
• Two full-screen GUI graphics layers in ARGB1555 or ARGB8888 format for DHD 0 and DHD 1
• One hardware cursor layer in ARGB1555 or ARGB8888 format (configurable), supporting a maximum resolution
of 256 x 256
• One scaling WBC channel
CV Hardware Accelerated Engine
• Hardware acceleration for binocular depth map computing, supporting the processing performance up to 720p@30 fps
• Hardware acceleration for IVE 2.1 intelligent operators for feature point detection, optical flow, and computer morphology processing, and so on
audio Interface
• Integrated audio codec, supporting 16-bit audio inputs and outputs
• Dual-channel differential MIC inputs for reducing the background noise
• I2S interface for 8-channel audio TDM inputs and dual- channel audio outputs (mutually exclusive with the built- in audio codec)
• HDMI audio output
Audio Encoding and Decoding
• Voice encoding and decoding complying with multiple protocols by software
• Audio encoding in formats such as G.711, G.726, and
file:///C:\Users\admin\AppData\Local\Temp\ksohtml8796\wps4.png−
AAC
−
VQE
−
Netw− ork Interface
• One GE interface:
RGMII and RMII modes
10/100 Mbit/s half-duplex or full-duplex 1000 Mbit/s full-duplex
TSO for reducing the CPU usage
Security Engine
• AES, DES, and 3DES algorithms implemented by using hardware
• RSA1024/2048/3072/4096 signature verification algorithm implemented by using hardware
• HASH-SHA1/224/256/384/512 and
HMAC_SHA1/224/256/384/512 tamper proofing algorithms implemented by using hardware
• file:///C:\Users\admin\AppData\Local\Temp\ksohtml8796\wps5.pngIntegrated 32-kbit OTP storage space and hardware random number generator
• file:///C:\Users\admin\AppData\Local\Temp\ksohtml8796\wps6.pngSecure boot
• memory and I/O security ISOlation
Peri−pheral Interface
• −Two SDIO 3.0 interfaces:
− SDIO 0 supports the SDXC card.
SDIO 1 supports the Wi-Fi module.
• One USB 3.0/PCIe 2.0 multiplexing port USB 3.0 only or PCIe 2.0 X1+USB 2.0.
RC and endpoint supported as the PCIe 2.0 interface Configurable USB host/device mode as the USB 3.0 interface
• One USB 2.0 port, supporting configurable host/device mode
• Internal POR signal output and external reset input
• Independent battery for the built-in RTC
• Integrated 4-channel LSADC
• Nine UART interfaces (Some pins are multiplexed with other pins.)
• Multiple I2C, SPI, and GPIO interfaces
• file:///C:\Users\admin\AppData\Local\Temp\ksohtml8796\wps7.pngOne IR interface
• Eight PWM interfaces (Some pins are multiplexed with other pins.)
−
External Memory Interface
• 3−2-bit DDR4/LPDDR4 SDRAM interface
− Maximum frequency of 1333 MHz for the
− DDR4/LPDDR4 SDRAM
Maximum DDR address space of 3.5 GB
• S−I NOR flash interface
− 1-/2-/4-line mode
− 3-/4-byte address mode
− Maximum capacity of 256 MB
• SPI NAND flash interface
− SLC flash
− 2 KB/4 KB page size
− 8-/24-bit ECC (unit: KB)
− Maximum capacity of 1 GB
• N− AND flash interface
8-bit data width
− SLC flash
− 2 KB/4 KB page size
8-/16-/24-bit ECC (unit: KB)
Maximum capacity of 1 GB
• EMMC 5.1 interface HS400
Maximum capacity of 2 TB
Configurable Boot Modes
• Booting from the BOOTROM
• Booting from the SPI NOR flash
• Booting from the SPI NAND flash
• Booting from the NAND flash
• Booting from an eMMC
Multiple Image Burning Modes
• Image burning through UART 0
• Image burning through an SD card
• Image burning through a USB device
SDK
• file:///C:\Users\admin\AppData\Local\Temp\ksohtml8796\wps8.pnglinux SMP
• Linux+Huawei LiteOS dual-system solution
• High-performance H.265 IOS/android decoding library
Phys−ical Specifications
• Power consumption
1.9 W power consumption in a typical scenario for 4K x 2K (3840 x 2160)@30 fps encoding+neural network algorithm
Multi-level power saving mode
• Operating voltages
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