1667
- 收藏
- 点赞
- 分享
- 举报
Hi3520V300 + NVP6134C 采用BT1120/720P接口VI没中断
Hi3520DV300 + NVP6134C,sample_vio跑的SAMPLE_VI_MODE_1_720P,始终没有Vi中断。
不知道是sample_vio设置问题,还是底层驱动的问题。
测了NVP6134C的数据信号和clk都是正常的。NVP6134C设置的Vclk是37.125M。
VI_DEV_ATTR_S 设置如下:
VI_DEV_ATTR_S DEV_ATTR_7441_BT1120_STANDARD_BASE =
{
/*interface mode*/
VI_MODE_BT1120_STANDARD,
/*work mode, 1/2/4 multiplex*/
VI_WORK_MODE_1Multiplex,
/* r_mask g_mask b_mask*/
{0xFF000000, 0xFF0000},
/* for single/double edge, must be set when double edge*/
VI_CLK_EDGE_SINGLE_UP,
/*AdChnId*/
{-1, -1, -1, -1},
/*enDataSeq, just support yuv*/
VI_INPUT_DATA_UVUV,
}
~ # cat /proc/umap/vi
[VIU] Version: [Hi3521A_MPP_V1.0.3.0 B040 Release], Build Time: [Dec 19 2015, 17:58:30]
-----MODULE PARAM--------------------------------------------------------------
detect_err_frame drop_err_frame stop_int_level max_cas_gap
10 0 0 28000
-----VI DEV ATTR---------------------------------------------------------------
Dev IntfM WkM ComMsk0 ComMsk1 CLKM AD0 AD1 AD2 AD3 Seq DPath DType DRev
0 BT1120S 1Mux ff ff0000 UP -1 -1 -1 -1 UVUV ByPass YUV N
-----VI HIGH DEV ATTR---------------------------------------------------------------
Dev InputM WkM ComMsk0 ComMsk1 AD0 AD1 AD2 AD3 Seq CombM CompM ClkM Fix FldP DPath DType DRev
-----VI PHYCHN ATTR------------------------------------------------------------
PhyChn CapX CapY CapW CapH DstW DstH CapSel ScanM SkipM Mirror Flip IntEn PixFom SrcRat DstRat
0 0 0 1280 720 1280 720 both P SKIPNON N N Y sp422 -1 -1
-----VI PHYCHN MINOR ATTR------------------------------------------------------------
PhyChn CapX CapY CapW CapH DstW DstH CapSel ScanM Mirror Flip PixFom MixCap DwScal SrcRat DstRat
-----VI PHYCHN STATUS 1----------------------------------------------------------
PhyChn BindDev Way IntCnt VbFail LosInt TopLos BotLos BufCnt IntT SendT Field Stride
0 0 0 0 0 0 0 0 0 0 0 (null) 0
-----VI PHYCHN STATUS 2---------------------------------------------------------
PhyChn MaxIntT IntGapT MaxGapT OverCnt LIntCnt ThrCnt AutoDis CasAutD TmgErr ccErrN IntRat
0 0 0 0 0 0 0 0 0 0 0 0
-----VI CHN STATUS-------------------------------------------------------------
ViChn bEnUsrP FrmTime FrmRate SendCnt SwLost Depth
0 N 0 0 0 0 0
-----VI CHN CALL VGS STATUS 1-------------------------------------------------
ViChn UsrBgnNOk UsrCancel UsrEndOk UsrCbOk CvrBgnNOk CvrCancel CvrEndOk CvrCbOk
-----VI CHN CALL VGS STATUS 2-------------------------------------------------
ViChn OsdBgnNOk OsdCancel OsdEndOk OsdCbOk ScaleNOk SclCancel SclEndOk SclCbOk
~ #
想问问大家,有能正常出图像的3520DV300 BT1120 接口的demo吗?
不知道是sample_vio设置问题,还是底层驱动的问题。
测了NVP6134C的数据信号和clk都是正常的。NVP6134C设置的Vclk是37.125M。
VI_DEV_ATTR_S 设置如下:
VI_DEV_ATTR_S DEV_ATTR_7441_BT1120_STANDARD_BASE =
{
/*interface mode*/
VI_MODE_BT1120_STANDARD,
/*work mode, 1/2/4 multiplex*/
VI_WORK_MODE_1Multiplex,
/* r_mask g_mask b_mask*/
{0xFF000000, 0xFF0000},
/* for single/double edge, must be set when double edge*/
VI_CLK_EDGE_SINGLE_UP,
/*AdChnId*/
{-1, -1, -1, -1},
/*enDataSeq, just support yuv*/
VI_INPUT_DATA_UVUV,
}
~ # cat /proc/umap/vi
[VIU] Version: [Hi3521A_MPP_V1.0.3.0 B040 Release], Build Time: [Dec 19 2015, 17:58:30]
-----MODULE PARAM--------------------------------------------------------------
detect_err_frame drop_err_frame stop_int_level max_cas_gap
10 0 0 28000
-----VI DEV ATTR---------------------------------------------------------------
Dev IntfM WkM ComMsk0 ComMsk1 CLKM AD0 AD1 AD2 AD3 Seq DPath DType DRev
0 BT1120S 1Mux ff ff0000 UP -1 -1 -1 -1 UVUV ByPass YUV N
-----VI HIGH DEV ATTR---------------------------------------------------------------
Dev InputM WkM ComMsk0 ComMsk1 AD0 AD1 AD2 AD3 Seq CombM CompM ClkM Fix FldP DPath DType DRev
-----VI PHYCHN ATTR------------------------------------------------------------
PhyChn CapX CapY CapW CapH DstW DstH CapSel ScanM SkipM Mirror Flip IntEn PixFom SrcRat DstRat
0 0 0 1280 720 1280 720 both P SKIPNON N N Y sp422 -1 -1
-----VI PHYCHN MINOR ATTR------------------------------------------------------------
PhyChn CapX CapY CapW CapH DstW DstH CapSel ScanM Mirror Flip PixFom MixCap DwScal SrcRat DstRat
-----VI PHYCHN STATUS 1----------------------------------------------------------
PhyChn BindDev Way IntCnt VbFail LosInt TopLos BotLos BufCnt IntT SendT Field Stride
0 0 0 0 0 0 0 0 0 0 0 (null) 0
-----VI PHYCHN STATUS 2---------------------------------------------------------
PhyChn MaxIntT IntGapT MaxGapT OverCnt LIntCnt ThrCnt AutoDis CasAutD TmgErr ccErrN IntRat
0 0 0 0 0 0 0 0 0 0 0 0
-----VI CHN STATUS-------------------------------------------------------------
ViChn bEnUsrP FrmTime FrmRate SendCnt SwLost Depth
0 N 0 0 0 0 0
-----VI CHN CALL VGS STATUS 1-------------------------------------------------
ViChn UsrBgnNOk UsrCancel UsrEndOk UsrCbOk CvrBgnNOk CvrCancel CvrEndOk CvrCbOk
-----VI CHN CALL VGS STATUS 2-------------------------------------------------
ViChn OsdBgnNOk OsdCancel OsdEndOk OsdCbOk ScaleNOk SclCancel SclEndOk SclCbOk
~ #
想问问大家,有能正常出图像的3520DV300 BT1120 接口的demo吗?
我来回答
回答0个
时间排序
认可量排序
暂无数据
或将文件直接拖到这里
悬赏:
E币
网盘
* 网盘链接:
* 提取码:
悬赏:
E币
Markdown 语法
- 加粗**内容**
- 斜体*内容*
- 删除线~~内容~~
- 引用> 引用内容
- 代码`代码`
- 代码块```编程语言↵代码```
- 链接[链接标题](url)
- 无序列表- 内容
- 有序列表1. 内容
- 缩进内容
- 图片![alt](url)
相关问答
-
2020-10-28 10:19:16
-
2015-08-28 09:55:56
-
2020-02-18 17:27:10
-
2017-11-17 11:49:01
-
2017-12-11 18:22:30
-
2018-07-16 10:14:48
-
2019-04-17 16:18:40
-
2017-03-21 10:45:45
-
2018-05-14 10:37:41
-
2017-08-08 16:18:20
-
2016-01-04 22:40:16
-
2020-12-28 19:13:14
-
2018-08-02 10:38:05
-
2017-04-27 10:07:48
-
2015-09-10 10:54:26
-
2020-05-09 18:26:57
-
2016-12-07 09:38:20
-
2019-03-28 14:24:26
-
2017-12-28 14:45:16
无更多相似问答 去提问
点击登录
-- 积分
-- E币
提问
—
收益
—
被采纳
—
我要提问
切换马甲
上一页
下一页
悬赏问答
-
50帮忙解决个交叉编译的问题
-
20帮忙交叉编译个源码
-
5Hi3516CV610 如何使用SD卡升级固件
-
5cat /dev/logmpp 报错 <3>[ vi] [func]:vi_send_frame_node [line]:99 [info]:vi pic queue is full!
-
50如何获取vpss chn的图像修改后发送至vo
-
5FPGA通过Bt1120传YUV422数据过来,vi接收不到数据——3516dv500
-
50SS928 运行PQtools 拼接 推到设备里有一半画面会异常
-
53536AV100的sample_vdec输出到CVBS显示
-
10海思板子mpp怎么在vi阶段改变视频数据尺寸
-
10HI3559AV100 多摄像头同步模式
举报反馈
举报类型
- 内容涉黄/赌/毒
- 内容侵权/抄袭
- 政治相关
- 涉嫌广告
- 侮辱谩骂
- 其他
详细说明
提醒
你的问题还没有最佳答案,是否结题,结题后将扣除20%的悬赏金
取消
确认
提醒
你的问题还没有最佳答案,是否结题,结题后将根据回答情况扣除相应悬赏金(1回答=1E币)
取消
确认