郁闷了，关于nvp6114。。。

本帖最后由 dhdahai 于 2015-12-7 20:56 编辑

6114的bank1寄存器0xCC 0xCD用来配置656输出clk

根据6114文档18页

Operated in the 54MHz(720H) / 72MHz(960H) 2-CH D1 Data Out Mode, NVP6114 outputs
VCLK01, VCLK02 and VDO1[7:0], VDO2[7:0] in the timing as shown in Figure 2.10. Two
channel video data stream represents 8bit BT.656/656like 4:2:2 format with 54MHz(720H) /
72MHz(960H) multiplexed. For VCLK01 and VCLK02 phase adjustment can be made against
VDO1~VDO2 using "Clock Delay Control" Register.
- (VCLK_x_SEL, 0xCC / CD[6:4], Bank1 = 0x40/0x50)
- (VCLK_x_DLY_SEL, 0xCC / CD[3:0], Bank1 = 0x40~0x5F)
- (CH_OUT_SELx, 0xC8[7:4] / 0xC8[3:0], Bank1 = 0x22)

0xCC/CD = 0x40时，clk为54M
0xCC/CD = 0x50时，clk为72M

可是我修改配置后，测试输出clk一直是72M。。。

要崩溃了。。。