芯片设计之CDC异步电路(五)_专栏

芯片设计之CDC异步电路(四)

芯片设计之CDC异步电路(三)

芯片设计之CDC异步电路(二)

芯片设计之CDC异步电路(一)

1 CDC常见错误

===

1.1 Reconvergence

1.1.1 single_source_reconvergence

结构：同一个信号源头，两个同步处理器。这里提一下，有两个CDC分析工具的参数配置：

1.1.2 案列1：divergence_depths为0

<pre class="code-snippet__js" data-lang="properties">```
<span class="code-snippet_outer"><span class="code-snippet__meta">//</span> <span class="code-snippet__string">divergence point</span></span>

always @ (posedge tx_clk)

<span class="code-snippet_outer">    <span class="code-snippet__attr">ctrl</span> <span class="code-snippet__string"></span></span>

<span class="code-snippet_outer"><span class="code-snippet__meta">//</span> <span class="code-snippet__string">two_dff synchronizer</span></span>

always @ (posedge rx_clk) begin: two_dff

<span class="code-snippet_outer">    <span class="code-snippet__attr">reg</span> <span class="code-snippet__string">temp;</span></span>

temp

<span class="code-snippet_outer">    <span class="code-snippet__attr">two_dff_sync</span> <span class="code-snippet__string"></span></span>

end

<span class="code-snippet_outer"> </span>

// shift_reg synchronizer

<span class="code-snippet_outer"><span class="code-snippet__attr">always</span> <span class="code-snippet__string">@ (posedge rx_clk) begin: shift_reg</span></span>

shift_reg_sync

<span class="code-snippet_outer"><span class="code-snippet__attr">end</span></span>

<span class="code-snippet_outer"><span class="code-snippet__meta">//</span> <span class="code-snippet__string">reconvergence point</span></span>

always @ (posedge rx_clk)

<span class="code-snippet_outer">    <span class="code-snippet__attr">dout</span> <span class="code-snippet__string"></span></span>

电路如下：divergence_depth为0

CDC报告如下：

1.2 Redundant

案例1：

<pre class="code-snippet__js" data-lang="properties">```
<span class="code-snippet_outer"><span class="code-snippet__meta">//</span> <span class="code-snippet__string">two_dff synchronizer of tx_sig</span></span>

always @ (posedge rx_clk) begin: two_dff

<span class="code-snippet_outer">    <span class="code-snippet__attr">reg</span> <span class="code-snippet__string">s0 , s1;</span></span>

<span class="code-snippet_outer">    <span class="code-snippet__attr">s1</span> <span class="code-snippet__string"></span></span>

end

<span class="code-snippet_outer"><br></br></span>

// two_dff synchronizer of tx_sig

<span class="code-snippet_outer"><span class="code-snippet__attr">always</span> <span class="code-snippet__string">@ (posedge rx_clk) begin: shift_reg</span></span>

reg [1:0] sh_reg;

<span class="code-snippet_outer">    <span class="code-snippet__meta">sh_reg =<span class="code-snippet__string"> {sh_reg[0], tx_sig};</span></span></span>

end

1.3 multi_sync_mux_select (DMUX)

MUX的sel端fan-in信号超过一组同步器，不推荐。通常MUX的sel端只能有一组同步器。

案例1：

<pre class="code-snippet__js" data-lang="properties">```
<span class="code-snippet_outer"><span class="code-snippet__attr">always</span> <span class="code-snippet__string">@(posedge rx_clk) begin</span></span>

reg s1_sel1, s2_sel1;

<span class="code-snippet_outer">    <span class="code-snippet__attr">reg</span> <span class="code-snippet__string">[1:0] s_sel2;</span></span>

<span class="code-snippet_outer">    <span class="code-snippet__attr">s1_sel1</span> <span class="code-snippet__string"></span></span>

s2_sel1

<span class="code-snippet_outer">    </span>

s_sel2

<span class="code-snippet_outer">    </span>

if (s_sel2[1] | s2_sel1)

<span class="code-snippet_outer"><span class="code-snippet__meta">        rx_data =<span class="code-snippet__string"> tx_data;</span></span></span>

end

电路如下：

1.4 combo_logic

1.4.1 错误案列1

<pre class="code-snippet__js" data-lang="properties">```
<span class="code-snippet_outer"><span class="code-snippet__attr">always</span> <span class="code-snippet__string">@ (posedge rx_clk) begin</span></span>

<span class="code-snippet_outer">    <span class="code-snippet__attr">s2</span> <span class="code-snippet__string"></span></span>

end

当然还有如下这种错误，除非additional logic全部是静态变量。

1.5 async_reset_no_sync（异步复位、同步撤离）

1.5.1 案列1

<pre class="code-snippet__js" data-lang="javascript">```
<span class="code-snippet_outer"><span class="code-snippet__comment">// Reset triggered by tx_clk</span></span>

always @(posedge tx_clk)

<span class="code-snippet_outer">tx_sig </span>

<span class="code-snippet_outer"><span class="code-snippet__comment">// Unsynchronized reset used in</span></span>

// Rx domain

<span class="code-snippet_outer">always @(posedge rx_clk,negedge tx_sig)</span>

if (!tx_sig) rx_sig 1’b0;

<span class="code-snippet_outer"><span class="code-snippet__keyword">else</span> rx_sig </span>


![](https://ebaina.oss-cn-hangzhou.aliyuncs.com/wechat-official-crawl/2022-01/164289961512959.jpg)

![](https://ebaina.oss-cn-hangzhou.aliyuncs.com/wechat-official-crawl/2022-01/164289961521047.jpg)

### 1.5.2 错误案列2

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```
// Reset triggered by tx_clk
``````
always @(posedge tx_clk)
``````
tx_sig 
``````
// Improperly synchronized reset used
``````
// in Rx domain
``````
always @(posedge rx_clk,negedge tx_sig)
``````
if (!tx_sig) rx_reset 1’b0;
``````
else rx_reset 1’b1;
```
```

![](https://ebaina.oss-cn-hangzhou.aliyuncs.com/wechat-official-crawl/2022-01/164289961577742.jpg)

![](https://ebaina.oss-cn-hangzhou.aliyuncs.com/wechat-official-crawl/2022-01/164289961586413.jpg)

正确的结构如下：

![](https://ebaina.oss-cn-hangzhou.aliyuncs.com/wechat-official-crawl/2022-01/16428996168866.jpg)

1.6 dff\_sync\_gated\_clk
-------------------------

![](https://ebaina.oss-cn-hangzhou.aliyuncs.com/wechat-official-crawl/2022-01/164289961614889.jpg)

 案列1，与门做时钟gating有毛刺，需要clock gating cell。
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```
```
// gated clock expression
``````
assign gclk = rx_clk & clk_en;
``````
always @(posedge gclk)
``````
    sync1 
``````
always @(posedge rx_clk)
``````
    sync2 
```
```

![](https://ebaina.oss-cn-hangzhou.aliyuncs.com/wechat-official-crawl/2022-01/164289961757064.jpg)

![](https://ebaina.oss-cn-hangzhou.aliyuncs.com/wechat-official-crawl/2022-01/164289961731244.jpg)

1.7 fanin\_different\_clks
--------------------------

同步器的输入由两个异步时钟域的组合逻辑构成，如下图所示：（还有combo logic）

![](https://ebaina.oss-cn-hangzhou.aliyuncs.com/wechat-official-crawl/2022-01/164289961869519.jpg)

值得注意的是，如果sig\_a或者sig\_b中有一个信号是stable静态变量，那么上图结构的电路就不会被报fanin\_different\_clks或者combo\_logic错误。

假设有sig\_a、sig\_b、sig\_c三个信号及以上的fan\_in呢？抛开静态变量后，

若所有信号都是同一个时钟域，CDC错误类型就是combo\_logic；

若所有信号来自至少2个时钟域，CDC错误类型就是fanin\_different\_clks；

举个例子，如下图：

![](https://ebaina.oss-cn-hangzhou.aliyuncs.com/wechat-official-crawl/2022-01/164289961894389.jpg)

上图电路仍会报fanin\_different\_clks，但是电路确实是设计者的意图，我们只需要将TEST时钟域的test\_sel设置为常数0即可。

### 1.7.1 案列1

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```
```
always @ (posedge tx1_clk)
``````
    tx1_sig 
``````
always @ (posedge tx2_clk)
``````
    tx2_sig 
``````
always @ (posedge rx_clk) begin
``````
    sync0 
``````
    sync1 
``````
end
```
```

![](https://ebaina.oss-cn-hangzhou.aliyuncs.com/wechat-official-crawl/2022-01/164289961836099.jpg)

![](https://ebaina.oss-cn-hangzhou.aliyuncs.com/wechat-official-crawl/2022-01/1642899619196.jpg)

时间不早了，暂写到这里，后续接着完善。

感谢阅读文章，如果文章有用，麻烦点个“在看”或转发分享。

![](https://ebaina.oss-cn-hangzhou.aliyuncs.com/wechat-official-crawl/2022-01/1642899619934.jpg)

转载：全栈芯片工程师